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? semiconductor components industries, llc, 2001 january, 2001 rev. 2 1 publication order number: cs51312/d cs51312 synchronous cpu buck controller for 12 v only applications the cs51312 is a synchronous dual nfet buck regulator controller. it is designed to power the core logic of the latest high performance cpus and asics from a single 12 v input. it uses the v 2 ? control method to achieve the fastest possible transient response and best overall regulation. it incorporates many additional features required to ensure the proper operation and protection of the cpu and power system. the cs51312 provides the industry's most highly integrated solution, minimizing external component count, total solution size, and cost. the cs51312 is specifically designed to power intel's pentium ? ii processor and includes the following features: 5bit dac with 1.2% tolerance, powergood output, overcurrent hiccup mode protection, overvoltage protection, v cc monitor, soft start, adaptive voltage positioning, adaptive fet nonoverlap time, and remote sense. the cs51312 will operate over a 9.0 v to 20 v (v cc2 ) range using either single or dual input voltage and is available in 16 lead narrow body surface mount package. features ? synchronous switching regulator controller for cpu v core ? dual nchannel mosfet synchronous buck design ? v 2 control topology ? 200 ns transient loop response ? 5bit dac with 1.2% tolerance ? hiccup mode overcurrent protection ? 40 ns gate rise and fall times (3.3 nf load) ? 65 ns adaptive fet nonoverlap time ? adaptive voltage positioning ? power good output monitors regulator output ? 5.0 v/12 v or 12 vonly operation ? v cc monitor provides undervoltage lockout ? ovp output monitors regulator output ? multifunctional comp pin provides enable, soft start, and hiccup timing in addition to control loop compensation http://onsemi.com device package shipping ordering information cs51312gd16 so16 48 units/rail cs51312gdr16 so16 2500 tape & reel pin connections marking diagram so16 d suffix case 751b a = assembly location wl, l = wafer lot yy, y = year ww, w = work week 1 cs51312 awlyww 16 1 16 v cc2 v cc1 1 16 gate(h) v out gnd v fb gate(l) v id4 ovp v id3 pwrgd v id2 c off v id1 comp v id0
cs51312 http://onsemi.com 2 figure 1. application diagram, 12 v to 16 a high performance converter fy10aaj03a l1 1.2 m h r4 0.004 w c off comp v id0 v id1 v id2 v id3 v id4 v fb gate(h) gate(l) gnd ovp pwrgd cs51312 v cc2 v out v cc1 c19 1000 pf c9 0.01 m f r2 200 c10 1.0 m f d2 zm4746actnd r1 22 w c1 1.0 m f + fy10aaj03a fy10aaj03a fy10aaj03a d3 ss12gictnd ovp pwrgd 1 1 dac enable r3 10 k 12 v 12 v 220 m f 16sv220 c6 0.01 m f q1 q4 q2 q3 d1 ss16gictnd t510x477k006as4394 + + + + + + + c2 c3 c4 c11 c12 c13 c14 c15 470 m f 470 m f 1.25 v to 3.5 v
cs51312 http://onsemi.com 3 absolute maximum ratings* rating value unit operating junction temperature, t j 150 c lead temperature soldering: reflow: (smd styles only) (note 1.) 230 peak c storage temperature range, t s 65 to +150 c esd susceptibility 2.0 kv 1. 60 second maximum above 183 c. *the maximum package power dissipation must be observed. absolute maximum ratings pin name pin symbol v max v min i source i sink ic bias and low side driver power input v cc1 16 0.3 n/a 1.5 a peak, 200 ma dc ic high side driver power input v cc2 20 v 0.3 v n/a 1.5 a peak, 200 ma dc compensation pin comp 6.0 v 0.3 v 1.0 ma 5.0 ma voltage feedback input, output voltage sense pin, voltage id dac inputs v fb , v out , v id04 6.0 v 0.3 v 1.0 ma 1.0 ma offtime pin c off 6.0 v 0.3 v 1.0 ma 50 ma highside fet driver gate(h) 20 v 0.3 v dc 1.5 a peak, 200 ma dc 1.5 a peak, 200 ma dc lowside fet driver gate(l) 16 v 0.3 v dc 1.5 a peak, 200 ma dc 1.5 a peak, 200 ma dc power good output pwrgd 6.0 v 0.3 v 1.0 ma 30 ma overvoltage protection ovp 15 v 0.3 v 30 ma 1.0 ma ground gnd 0 v 0 v 1.5 a peak, 200 ma dc n/a
cs51312 http://onsemi.com 4 electrical characteristics (0 c < t a < 70 c; 0 c < t j < 125 c; 9.0 v < v cc1 < 14 v; 9.0 v v cc2 20 v; 2.0 v dac code (v id4 = v id3 = v id2 = v id1 = 0, v id0 = 1.0) c gate(h) = c gate(l) = 3.3 nf, c off = 390 pf; unless otherwise specified.) characteristic test conditions voltage identification dac measure v fb = v comp , v cc = 12 v. note 2. 75 c t j 125 c 25 c t j 75 c v id4 v id3 v id2 v id1 v id0 min typ max tol min typ max tol unit 1 0 0 0 0 3.483 3.525 3.567 1.2% 3.455 3.525 3.596 2.0% v 1 0 0 0 1 3.384 3.425 3.466 1.2% 3.357 3.425 3.494 2.0% v 1 0 0 1 0 3.285 3.325 3.365 1.2% 3.259 3.325 3.392 2.0% v 1 0 0 1 1 3.186 3.225 3.264 1.2% 3.161 3.225 3.290 2.0% v 1 0 1 0 0 3.087 3.125 3.163 1.2% 3.063 3.125 3.188 2.0% v 1 0 1 0 1 2.989 3.025 3.061 1.2% 2.965 3.025 3.086 2.0% v 1 0 1 1 0 2.890 2.925 2.960 1.2% 2.875 2.925 2.975 1.7% v 1 0 1 1 1 2.791 2.825 2.859 1.2% 2.777 2.825 2.873 1.7% v 1 1 0 0 0 2.692 2.725 2.758 1.2% 2.679 2.725 2.771 1.7% v 1 1 0 0 1 2.594 2.625 2.657 1.2% 2.580 2.625 2.670 1.7% v 1 1 0 1 0 2.495 2.525 2.555 1.2% 2.482 2.525 2.568 1.7% v 1 1 0 1 1 2.396 2.425 2.454 1.2% 2.389 2.425 2.461 1.5% v 1 1 1 0 0 2.297 2.325 2.353 1.2% 2.290 2.325 2.360 1.5% v 1 1 1 0 1 2.198 2.225 2.252 1.2% 2.192 2.225 2.258 1.5% v 1 1 1 1 0 2.099 2.125 2.151 1.2% 2.093 2.125 2.157 1.5% v 0 0 0 0 0 2.050 2.075 2.100 1.2% 2.044 2.075 2.106 1.5% v 0 0 0 0 1 2.001 2.025 2.049 1.2% 1.995 2.025 2.055 1.5% v 0 0 0 1 0 1.953 1.975 1.997 1.1% 1.945 1.975 2.005 1.5% v 0 0 0 1 1 1.904 1.925 1.946 1.1% 1.896 1.925 1.954 1.5% v 0 0 1 0 0 1.854 1.875 1.896 1.1% 1.847 1.875 1.903 1.5% v 0 0 1 0 1 1.805 1.825 1.845 1.1% 1.798 1.825 1.852 1.5% v 0 0 1 1 0 1.755 1.775 1.795 1.1% 1.748 1.775 1.802 1.5% v 0 0 1 1 1 1.706 1.725 1.744 1.1% 1.699 1.725 1.751 1.5% v 0 1 0 0 0 1.656 1.675 1.694 1.1% 1.650 1.675 1.700 1.5% v 0 1 0 0 1 1.607 1.625 1.643 1.1% 1.601 1.625 1.649 1.5% v 0 1 0 1 0 1.558 1.575 1.593 1.1% 1.551 1.575 1.599 1.5% v 0 1 0 1 1 1.508 1.525 1.542 1.1% 1.502 1.525 1.548 1.5% v 0 1 1 0 0 1.459 1.475 1.491 1.1% 1.453 1.475 1.497 1.5% v 0 1 1 0 1 1.409 1.425 1.441 1.1% 1.404 1.425 1.446 1.5% v 0 1 1 1 0 1.360 1.375 1.390 1.1% 1.354 1.375 1.396 1.5% v 0 1 1 1 1 1.310 1.325 1.340 1.1% 1.305 1.325 1.345 1.5% v 1 1 1 1 1 1.225 1.250 1.275 2.0% 1.225 1.250 1.275 2.0% v 2. the ic power dissipation in a typical application with v cc = 12 v, switching frequency f sw = 250 khz, 50 nc mosfets and r q ja = 115 c/w yields an operating junction temperature rise of approximately 52 c, and a junction temperature of 77 c with an ambient temperature of 25 c.
cs51312 http://onsemi.com 5 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 9.0 v < v cc1 < 14 v; 9.0 v v cc2 20 v; 2.0 v dac code (v id4 = v id3 = v id2 = v id1 = 0, v id0 = 1.0) c gate(h) = c gate(l) = 3.3 nf, c off = 390 pf; unless otherwise specified.) characteristic test conditions min typ max unit voltage identification dac (continued) line regulation 9.0 v v cc 14 v 0.01 %/v input threshold v id4 , v id3 , v id2 , v id1 , v id0 1.0 1.25 2.4 v input pullup resistance v id4 , v id3 , v id2 , v id1 , v id0 25 50 100 k w pullup voltage 5.48 5.65 5.82 v error amplifier v fb bias current 0.2 v v fb 3.5 v 7.0 0.1 7.0 m a comp source current v comp = 1.2 v to 3.6 v, v fb = 1.9 v 15 30 60 m a comp sink current v comp = 1.2 v, v fb = 2.1 v 30 60 120 m a open loop gain c comp = 0.1 m f 80 db unity gain bandwidth c comp = 0.1 m f 50 khz psrr @ 1.0 khz c comp = 0.1 m f 70 db transconductance 32 mmho output impedance 0.5 m w gate(h) and gate(l) high voltage at 100 ma measure v cc1/2 gate(l)/(h) 1.2 2.1 v low voltage at 100 ma measure gate(l)/(h) 1.0 1.5 v rise time 1.6 v < gate(h)/(l) < (v cc1/2 2.5 v) 40 80 ns fall time (v cc1/2 2.5 v) > gate(l)/(h) > 1.6 v 40 80 ns gate(h) to gate(l) delay gate(h) < 2.0 v, gate(l) > 2.0 v, v cc1/2 = 12 v 30 65 110 ns gate(l) to gate(h) delay gate(l) < 2.0 v, gate(h) > 2.0 v, v cc1/2 = 12 v 30 65 110 ns gate pulldown resistance to gnd. note 3. 20 50 115 k w overcurrent protection ovc comparator offset voltage 0 v v out 3.5 v 77 86 101 mv discharge threshold voltage 0.2 0.25 0.3 v v out bias current 0.2 v v out 3.5 v 7.0 0.1 7.0 m a ovc latch discharge current v comp = 1.0 v 100 800 2500 m a pwm comparator pwm comparator offset voltage 0 v v fb 3.5 v 0.99 1.1 1.23 v transient response v fb = 0 to 3.5 v 200 300 ns c off offtime 1.0 1.6 2.3 m s charge current v coff = 1.5 v 550 m a discharge current v coff = 1.5 v 25 ma 3. guaranteed by design, not 100% tested in production.
cs51312 http://onsemi.com 6 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 9.0 v < v cc1 < 14 v; 9.0 v v cc2 20 v; 2.0 v dac code (v id4 = v id3 = v id2 = v id1 = 0, v id0 = 1.0) c gate(h) = c gate(l) = 3.3 nf, c off = 390 pf; unless otherwise specified.) characteristic unit max typ min test conditions power good output pwrgd sink current v fb = 1.7 v, v pwrgd = 1.0 v 0.5 4.0 15 ma pwrgd upper threshold % of nominal dac code 5.0 8.5 12 % pwrgd lower threshold % of nominal dac code 12 8.5 5.0 % pwrgd output low voltage v fb = 1.7 v, i pwrgd = 500 m a 0.2 0.3 v overvoltage protection (ovp) output ovp source current ovp = 1.0 v 1.0 10 25 ma ovp threshold % of nominal dac code 5.0 8.5 12 % ovp pullup voltage i ovp = 1.0 ma, v cc1 v ovp 1.1 1.5 v general electrical specifications v cc1 monitor start threshold 7.9 8.4 8.9 v v cc1 monitor stop threshold 7.6 8.1 8.6 v hysteresis startstop 0.15 0.3 0.6 v v cc1 supply current no load on gate(h), gate(l) 9.5 16 ma v cc2 supply current no load on gate(h), gate(l) 2.5 4.5 ma package pin description package pin # so16 pin symbol function 1, 2, 3, 4, 5 v id0 v id4 voltage id dac inputs. these pins are internally pulled up to 5.65 v if left open. v id4 selects the dac range. when v id4 is high (logic one), the error amp reference range is 2.125 v to 3.525 v with 100 mv increments. when v id4 is low (logic zero), the error amp reference voltage is 1.325 v to 2.075 v with 50 mv increments. 6 v fb error amp inverting input, pwm comparator noninverting input, current limit comparator noninverting input, pwrgd and ovp comparator input. 7 v out current limit comparator inverting input. 8 v cc1 input power supply pin for the internal circuitry and low side gate driver. decou- ple with filter capacitor to gnd. 9 v cc2 input power supply pin for the high side gate driver. decouple with filter capaci- tor to gnd. 10 gate(h) high side switch fet driver pin. 11 gnd ground pin and ic substrate connection. 12 gate(l) low side synchronous fet driver pin. 13 ovp overvoltage protection pin. drives high when overvoltage condition is detected on v fb . 14 pwrgd power good output. open collector output drives low when v fb is out of regu- lation. 15 c off offtime capacitor pin. a capacitor from this pin to gnd sets the off time for the regulator. 16 comp error amp output. pwm comparator inverting input. a capacitor on this pin pro- vides error amp compensation, and determines the soft start and hiccup tim- ing. pulling comp below 1.1 v (typ) turns off both gate drivers and shuts down the regulator.
cs51312 http://onsemi.com 7 figure 2. block diagram + + + + current limit + + + + + v fb v out v id0 v id1 v id2 v id3 v id4 1.1 v 86 mv ea dac comp c off pwm comp discharge comp 0.25 v fault latch r s q off time uvlo v cc1 gate(h) gate(l) nonoverlap logic v cc ovp pwrgd gnd v cc2
cs51312 http://onsemi.com 8 typical performance characteristics 150 125 100 75 50 0 falltime (ns) 0 4000 8000 load capacitance (pf) 25 12000 16000 2000 6000 10000 14000 150 125 100 75 50 0 risetime (ns) 0 4000 8000 load capacitance (pf) 25 12000 16000 2000 6000 10000 14000 v cc = 12 v t a = 25 c v cc = 12 v t a = 25 c 0.10 0.05 0 0.05 0.10 0.15 dac output voltage deviation (%) 0 40 80 load capacitance (pf) 120 20 60 100 v cc = 12 v 0.10 0.05 0 0.05 0.10 0.20 output error (%) 1.325 dac output voltage setting (v) 0.15 1.375 1.425 1.475 1.525 1.575 1.625 1.675 1.725 1.775 1.825 1.875 1.925 1.975 2.025 2.075 0.35 0.25 0.15 0.05 0.05 0.25 output error (%) 2.125 0.15 dac output voltage setting (v) 0.30 0.20 0.10 0 0.10 0.20 2.225 2.325 2.425 2.525 2.625 2.725 2.825 2.925 3.025 3.125 3.225 3.325 3.425 3.525 figure 3. gate(h) and gate(l) falltime vs. load capacitance figure 4. gate(h) and gate(l) risetime vs. load capacitance figure 5. dac output voltage vs. temperature, dac code = 00001 figure 6. percent output error vs. dac output voltage setting, v id4 = 0 figure 7. percent output error vs. dac output voltage setting, v id4 = 1 v cc = 12 v t a = 25 c v id4 = 0 v cc = 12 v t a = 25 c v id4 = 1
cs51312 http://onsemi.com 9 applications information theory of operation v 2 control method the v 2 method of control uses a ramp signal that is generated by the esr of the output capacitors. this ramp is proportional to the ac current through the main inductor and is offset by the value of the dc output voltage. this control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. this control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current. the v 2 control method is illustrated in figure 8. the output voltage is used to generate both the error signal and the ramp signal. since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of that change. the ramp signal also contains the dc portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. figure 8. v 2 control diagram + + c e pwm comparator ramp signal comp error amplifier error signal reference voltage output voltage feedback v fb gate(h) gate(l) a change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the v 2 control scheme to compensate the duty cycle. since the change in inductor current modifies the ramp signal, as in current mode control, the v 2 control scheme has the same advantages in line transient response. a change in load current will have an affect on the output voltage, altering the ramp signal. a load step immediately changes the state of the comparator output, which controls the main switch. load transient response is determined only by the comparator response time and the transition speed of the main switch. the reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. the error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. the main purpose of this `slow' feedback loop is to provide dc accuracy. noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. line and load regulation are drastically improved because there are two independent voltage loops. a voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. this change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. a current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. the v 2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load. constant offtime to minimize transient response, the cs51312 uses a constant offtime method to control the rate of output pulses. during normal operation, the offtime of the high side switch is terminated after a fixed period, set by the c off capacitor. every time the v fb pin exceeds the comp pin voltage an offt ime is initiated. to maintain regulation, the v 2 control loop varies switch ontime. the pwm comparator monitors the output voltage ramp, and terminates the switch ontime. constant offtime provides a number of advantages. switch duty cycle can be adjusted from 0 to 100% on a pulseby pulse basis when responding to transient conditions. both 0% and 100% duty cycle operation can be maintained for extended periods of time in response to load or line transients. programmable output the cs51312 is designed to provide two methods for programming the output voltage of the power supply. a five bit on board digital to analog converter (dac) is used to program the output voltage within two different ranges. the first range is 2.125 v to 3.525 v in 100 mv steps, the second is 1.325 v to 2.075 v in 50 mv steps, depending on the digital input code. if all five bits are left open, the cs51312 enters adjust mode. in adjust mode, the designer can choose any output voltage by using resistor divider feedback to the v fb pin, as in traditional controllers. the cs51312 is specifically designed to meet or exceed intel's pentium ii specifications. error amplifier the comp pin is the output of the error amplifier. a capacitor to gnd compensates the error amplifier loop. additionally, the built in offset on the pwm comparator
cs51312 http://onsemi.com 10 noninverting input provides the hiccup timing for the overcurrent protection, soft start function, and regulator output enable. v cc2 charge pump in order to fully turn on the high side nfet, a voltage greater than the input voltage must be applied to v cc2 to bias the gate(h) driver. referring to the application diagram on page 2; a simple charge pump circuit can be implemented for this purpose through capacitor c6, resistor r1, and diodes d1 and d2. the input voltage, less the drop in d1 is stored in c6 during the of ftime period. when the highside fet turns on, it drives the inductor switching node and c6 high causing schottky diode d1 to reverse bias. the charge stored in c6 is transferred to v cc2 through r1. zener diode d2 clamps the v cc2 voltage to 18 v to prevent the v cc2 from exceeding its 20 v max rating (see figure 9). figure 9. v cc2 charge pump operation (1.0 s/div) channel 1 charge pump switching node (10 v/div) channel 2 v cc2 (10 v/div) channel 3 gate(h) (10 v/div) channel 4 inductor switching node (10 v/div) startup the cs51312 provides a controlled startup of regulator output voltage and features programmable soft start implemented through the error amp and external compensation capacitor. this feature, combined with overcurrent protection, prevents stress to the regulator power components and overshoot of the output voltage during startup. as power is applied to the regulator, the cs51312 undervoltage lockout circuit (uvl) monitors the ics supply voltage (v cc1 ) which is typically connected to the +12 v input. the uvl circuit prevents the nfet gates from being activated until v cc1 exceeds the 8.4 v (typ) threshold. hysteresis of 300 mv (typ) is provided for noise immunity. the error amp capacitor connected to the comp pin is charged by a 30 m a current source. this capacitor must be charged to 1.1 v (typ) so that it exceeds the pwm comparator's offset before the v 2 pwm control loop permits switching to occur. when v cc1 has exceeded 8.4 v and comp has charged to 1.1 v, the upper gate driver (gate(h)) is activated, turning on the upper fet. this causes current to flow through the output inductor and into the output capacitors and load according to the following equation: i (v in v out ) t l gate(h) and the upper nfet remain on and inductor current ramps up until the initial pulse is terminated by either the pwm control loop or the overcurrent protection. this initial surge of inrush current minimizes startup time, but avoids overstressing of the regulator's power components. the pwm comparator will terminate the initial pulse if the regulator output exceeds the voltage on the comp pin plus the 1.1 v pwm comparator offset prior to the drop across the current sense resistor exceeding the current limit threshold. in this case, the pwm control loop has achieved regulation and the initial pulse is then followed by a constant off time as programmed by the c off capacitor. the comp capacitor will continue to slowly charge and the regulator output voltage will follow it, less the 1.1 v pwm of fset, until it achieves the voltage programmed by the dac's vid input. the error amp will then source or sink current to the comp cap as required to maintain the correct regulator dc output voltage. since the rate of increase of the comp pin voltage is typically set much slower than the regulator's slew capability, inrush current, output voltage, and duty cycle all gradually increase from zero. (see figures 10 and 11). figure 10. normal startup (5.0 ms/div) channel 1 regulator input voltage and v cc1 (10 v/div) channel 2 comp (2.0 v/div) channel 3 regulator output voltage (1.0 v/div)
cs51312 http://onsemi.com 11 figure 11. normal startup showing initial pulse followed by soft start (5.0 s/div) channel 1 v cc2 (10 v/div) channel 2 gate(h) (10 v/div) channel 3 inductor switching node (10 v/div) channel 4 regulator output voltage (2.0 v/div) if the voltage across the current sense resistor generates a voltage difference between the v fb and v out pins that exceeds the ovc comparator offset voltage (86 mv typical), the fault latch is set. this causes the comp pin to be quickly discharged, turning off gate(h) and the upper nfet since the voltage on the comp pin is now less than the 1.1 v pwm comparator offset. the fault latch is reset when the voltage on the comp decreases below the discharge threshold voltage (0.25 v typical). the comp capacitor will again begin to charge, and when it exceeds the 1.1 v pwm comparator offset, the regulator output will soft start normally (see figure 12). figure 12. startup with comp precharged to 2.0 v (2.0 ms/div) channel 1 regulator output voltage (1.0 v/div) channel 2 comp pin (1.0 v/div) channel 3 v cc (10 v/div) when driving large capacitive loads, the comp must charge slowly enough to avoid tripping the cs51312 overcurrent protection. the following equation can be used to ensure unconditional startup: i chg c comp i lim i load c out where: i chg = comp source current (30 m a typical); c comp = comp capacitor value (0.1 m f typical); i lim = current limit threshold; i load = load current during startup; c out = total output capacitance. normal operation during normal operation, switch offtime is constant and set by the c off capacitor. switch ontime is adjusted by the v 2 control loop to maintain regulation. this results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. output voltage ripple will be determined by inductor ripple current and the esr of the output capacitors transient response the cs51312 v 2 control loop's 200 ns reaction time provides unprecedented transient response to changes in input voltage or output current. pulsebypulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. overall load transient response is further improved through a feature called aadaptive voltage positioningo. this technique prepositions the output capacitors voltage to reduce total output voltage excursions during changes in load. holding tolerance to 1.0% allows the error amplifiers reference voltage to be targeted +25 mv high without compromising dc accuracy. a adroop resistoro connects the error amps feedback pin (v fb ) to the output capacitors and load and carries the output current. with no load, there is no dc drop across this resistor, producing an output voltage tracking the error amps, including the +25 mv offset. when the full load current is delivered, a 50 mv drop is developed across this resistor. this results in output voltage being offset 25 mv low. the benefit of adaptive voltage positioning is that additional margin is provided for a load transient before reaching the output voltage specification limits. when load current suddenly increases from its minimum level, the output capacitor is prepositioned +25 mv. conversely, when load current suddenly decreases from its maximum level, the output capacitor is prepositioned 25 mv. for
cs51312 http://onsemi.com 12 best transient response, a combination of a number of high frequency and bulk output capacitors are usually used. protection and monitoring features overcurrent protection a hiccup mode current limit protection feature is provided, requiring only the comp capacitor to implement. the cs51312 provides overcurrent protection by sensing the current through a adroopo resistor, using an internal current sense comparator. the comparator compares the voltage drop through the adroopo resistor to an internal reference voltage of 86 mv (typical). if the voltage drop across the adroopo resistor exceeds this threshold, the current sense comparator allows the fault latch to be set. this causes the regulator to stop switching. during this over current condition, the cs51312 stays off for the time it takes the comp pin capacitor to discharge to its lower 0.25 v threshold. as soon as the comp pin reaches 0.25 v, the fault latch is reset (no overcurrent condition present) and the comp pin is char ged with a 30 m a current source to a voltage 1.1 v greater than the v fb voltage. only at this point the regulator attempts to restart normally by delivering short gate pulses to both fets. this protection scheme minimizes thermal stress to the regulator components, input power supply, and pc board traces, as the over current condition persists. upon removal of the overload, the fault latch is cleared, allowing normal operation to resume. overvoltage protection overvoltage protection (ovp) is provided as result of the normal operation of the v 2 control topology and requires no additional external components. the control loop responds to an overvoltage condition within 200 ns, causing the top mosfet to shut off, disconnecting the regulator from its input voltage. this results in a acrowbaro action to clamp the output voltage and prevents damage to the load. the regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. additionally, a dedicated overvoltage protection (ovp) output pin (pin 13) is provided in the cs51312. the ovp signal will go high (overvoltage condition), if the output voltage (v cc(core) ) exceeds the regulation voltage by 8.5% of the voltage set by the particular dac code. the ovp pin can source up to 25 ma of current that can be used to drive an scr to crowbar the power supply. power good circuit the power good pin (pin 14) is an opencollector signal consistent with ttl dc specifications. it is externally pulled up, and is pulled low (below 0.3 v) when the regulator output voltage typically exceeds 8.5% of the nominal output voltage. maximum output voltage deviation before power good is pulled low is 12%. output enable on/off control of the regulator outputs can be implemented by pulling the comp pins low. it is required to pull the comp pins below the 1.1 v pwm comparator offset voltage in order to disable switching on the gate drivers. adaptive fet nonoverlap the cs51312 includes circuitry to prevent the simultaneous conduction of both the high and low side nfets. this is necessary to prevent efficiency reducing ashootthrougho current from flowing from the input voltage to ground through the two nfets. prior to either gate(h) or gate(l) driving high, the other gate must reach its low state. since gate rise and fall times vary with loading, this results in a variable delay from the start of turnoff until the start of turnon (see figure 13). figure 13. adaptive fet nonoverlap (100 ns/div) channel 1 gate(h) (5.0 v/div) channel 2 gate(l) (5.0 v/div) channel 3 inductor switching node (10 v/div) cs51312based v cc(core) buck regulator design example step 1: definition of the design specifications the output voltage tolerance can be affected by any or all of the following reasons: 1. buck regulator output voltage setpoint accuracy; 2. output voltage change due to discharging or charging of the bulk decoupling capacitors during a load current transient; 3. output voltage change due to the esr and esl of the bulk and high frequency decoupling capacitors, circuit traces, and vias; 4. output voltage ripple and noise. budgeting the tolerance is left up to the designer who must take into account all of the above effects and provide an
cs51312 http://onsemi.com 13 output voltage that will meet the specified tolerance at the load. the designer must also ensure that the regulator component temperatures are kept within the manufacturer's specified ratings at full load and maximum ambient temperature.. step 2: selection of the output capacitors these components must be selected and placed carefully to yield optimal results. capacitors should be chosen to provide acceptable ripple on the regulator output voltage. key specifications for output capacitors are their esr (equivalent series resistance), and esl (equivalent series inductance). for best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. in order to determine the number of output capacitors the maximum voltage transient allowed during load transitions has to be specified. the output capacitors must hold the output voltage within these limits since the inductor current can not change with the required slew rate. the output capacitors must therefore have a very low esl and esr. the voltage change during the load current transient is: v out i out esl t esr t tr c out where: d i out / d t = load current slew rate; d i out = load transient; d t = load transient duration time; esl = maximum allowable esl including capacitors, circuit traces, and vias; esr = maximum allowable esr including capacitors and circuit traces; t tr = output voltage transient response time. the designer has to independently assign values for the change in output voltage due to esr, esl, and output capacitor discharging or charging. empirical data indicates that most of the output voltage change (droop or spike depending on the load current transition) results from the total output capacitor esr. the maximum allowable esr can then be determined according to the formula esr max v esr i out where d v esr = change in output voltage due to esr (assigned by the designer). once the maximum allowable esr is determined, the number of output capacitors can be found by using the formula number of capacitors esr cap esr max where: esr cap = maximum esr per capacitor (specified in manufacturer's data sheet); esr max = maximum allowable esr. the actual output voltage deviation due to esr can then be verified and compared to the value assigned by the designer: v esr i out esr max similarly, the maximum allowable esl is calculated from the following formula: esl max v esl t i where: d i/ d t = load current slew rate (as high as 20 a/ m s); d v esl = change in output voltage due to esl. the actual maximum allowable esl can be determined by using the equation: esl max esl cap number of output capacitors where esl cap = maximum esl per capacitor (it is estimated that a 10 12 mm aluminum electrolytic capacitor has approximately 4.0 nh of package inductance). the actual output voltage deviation due to the actual maximum esl can then be verified: v esl esl max i t the designer now must determine the change in output voltage due to output capacitor discharge during the transient: v cap i t tr c out where: d t tr = the output voltage transient response time (assigned by the designer); d v cap = output voltage deviation due to output capacitor discharge; d i = load step. the total change in output voltage as a result of a load current transient can be verified by the following formula: v out v esr v esl v cap step 3: selection of the duty cycle, switching frequency, switch ontime (t on ) and switch offtime (t off ) the duty cycle of a buck converter (including parasitic losses) is given by the formula: duty cycle d v out (v hfet v l v droop ) v in v lfet v hfet v l where: v out = buck regulator output voltage; v hfet = high side fet voltage drop due to r ds(on) ; v l = output inductor voltage drop due to inductor wire dc resistance;
cs51312 http://onsemi.com 14 v droop = droop (current sense) resistor voltage drop; v in = buck regulator input voltage; v lfet = low side fet voltage drop due to r ds(on) . step3a: calculation of switch ontime the switch ontime (time during which the switching mosfet in a synchronous buck topology is conducting) is determined by: t on duty cycle f sw where f sw = regulator switching frequency selected by the designer. higher operating frequencies allow the use of smaller inductor and capacitor values. nevertheless, it is common to select lower frequency operation because a higher frequency results in lower efficiency due to mosfet gate charge losses. additionally, the use of smaller inductors at higher frequencies results in higher ripple current, higher output voltage ripple, and lower efficiency at light load currents. step 3b: calculation of switch offtime the switch offtime (time during which the switching mosfet is not conducting) can be determined by: t off 1.0 f sw t on the c off capacitor value has to be selected in order to set the offtime, t off , above: c off period (1.0 d) 3980 where: 3980 is a characteristic factor of the cs51312; d = duty cycle. step 4: selection of the output inductor the inductor should be selected based on its inductance, current capability, and dc resistance. increasing the inductor value will decrease output voltage ripple, but degrade transient response. there are many factors to consider in selecting the inductor including cost, efficiency, emi and ease of manufacture. the inductor must be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. there are a variety of materials and types of magnetic cores that could be used for this application. among them are ferrites, molypermalloy cores (mpp), amorphous and powdered iron cores. powdered iron cores are very commonly used. powdered iron cores are very suitable due to their high saturation flux density and have low loss at high frequencies, a distributed gap and exhibit very low emi. the inductor value can be determined by: l (v in v out ) t tr i where: v in = input voltage; v out = output voltage; t tr = output voltage transient response time (assigned by the designer); d i = load transient. the inductor ripple current can then be determined: i l v out t off l where: d i l = inductor ripple current; v out = output voltage; t off = switch offtime; l = inductor value. the designer can now verify if the number of output capacitors from step 2 will provide an acceptable output voltage ripple (1.0% of output voltage is common). the formula below is used: i l v out esr max rearranging we have: esr max v out i l where esr max = maximum allowable esr; d v out = 1.0% v out = maximum allowable output voltage ripple ( budgeted by the designer ); d i l = inductor ripple current; v out = output voltage. the number of output capacitors is determined by: number of capacitors esr cap esr max where esr cap = maximum esr per capacitor (specified in manufacturer's data sheet). the designer must also verify that the inductor value yields reasonable inductor peak and valley currents (the inductor current is a triangular waveform): i l(peak) i out i l 2.0 where: i l(peak) = inductor peak current; i out = load current; d i l = inductor ripple current. i l(valley) i out i l 2.0 where i l(valley) = inductor valley current. step 5: selection of the input capacitors these components must be selected and placed carefully to yield optimal results. capacitors should be chosen to
cs51312 http://onsemi.com 15 provide acceptable ripple on the input supply lines. a key specification for input capacitors is their ripple current rating. the input capacitor should also be able to handle the input rms current i in(rms) . the combination of the input capacitors c in discharges during the ontime. the input capacitor discharge current is given by: i cindis(rms) i l(peak) 2 ( i l(peak) i l(valley) ) i l(valley) 2 d 3.0
where: i cindis(rms) = input capacitor discharge current; i l(peak) = inductor peak current; i l(valley) = inductor valley current. c in charges during the offtime, the average current through the capacitor over one switching cycle is zero: i cin(ch) i cin(dis) d 1.0 d where: i cin(ch) = input capacitor charge current; i cin(dis) = input capacitor discharge current; d = duty cycle. the total input rms current is: i cin(rms) ( i cin(dis) 2 d ) ( i cin(ch) 2 (1.0 d) )
the number of input capacitors required is then determined by: n cin i cin(rms) i ripple where: n cin = number of input capacitors; i cin(rms) = total input rms current; i ripple = input capacitor ripple current rating (specified in manufacturer's data sheets). the total input capacitor esr needs to be determined in order to calculate the power dissipation of the input capacitors: esr cin esr cap n cin where: esr cin = total input capacitor esr; esr cap = maximum esr per capacitor (specified in manufacturer's data sheets); n cin = number of input capacitors. once the total esr of the input capacitors is known, the input capacitor ripple voltage can be determined using the formula: v cin(rms) i cin(rms) esr cin where: v cin(rms) = input capacitor rms voltage; i cin(rms) = total input rms current; esr cin = total input capacitor esr. the designer must determine the input capacitor power loss in order to ensure there isn't excessive power dissipation through these components. the following formula is used: p cin(rms) i cin(rms) 2 esr cin where: p cin(rms) = input capacitor rms power dissipation; i cin(rms) = total input rms current; esr cin = total input capacitor esr. step 6: selection of the input inductor a common requirement is that the buck controller must not disturb the input voltage. one method of achieving this is by using an input inductor and a bypass capacitor. the input inductor isolates the supply from the noise generated in the switching portion of the buck regulator and also limits the inrush current into the input capacitors upon power up. the inductor's limiting effect on the input current slew rate becomes increasingly beneficial during load transients. the worst case is when the load changes from no load to full load (load step), a condition under which the highest voltage change across the input capacitors is also seen by the input inductor. the inductor successfully blocks the ripple current while placing the transient current requirements on the input bypass capacitor bank, which has to initially support the sudden load change. the minimum inductance value for the input inductor is therefore: l in v (di dt) max where: l in = input inductor value; d v = voltage seen by the input inductor during a full load swing; (di/dt) max = maximum allowable input current slew rate. the designer must select the lc filter pole frequency so that at least 40 db attenuation is obtained at the regulator switching frequency. the lc filter is a doublepole network with a slope of 2.0, a rolloff rate of e40 db/dec, and a corner frequency: f c 1.0 2.0 lc

cs51312 http://onsemi.com 16 where: l = input inductor; c = input capacitor(s). step 7: selection of the switching fet fet basics the use of the mosfet as a power switch is propelled by two reasons: 1) its very high input impedance; and 2) its very fast switching times. the electrical characteristics of a mosfet are considered to be those of a perfect switch. control and drive circuitry power is therefore reduced. because the input impedance is so high, it is voltage driven. the input of the mosfet acts as if it were a small capacitor, which the driving circuit must charge at turn on. the lower the drive impedance, the higher the rate of rise of v gs , and the faster the turnon time. power dissipation in the switching mosfet consists of 1) conduction losses, 2) leakage losses, 3) turnon switching losses, 4) turnoff switching losses, and 5) gatetransitions losses. the latter three losses are proportional to frequency. for the conducting power dissipation rms values of current and resistance are used for true power calculations. the fast switching speed of the mosfet makes it indispensable for highfrequency power supply applications. not only are switching power losses minimized, but also the maximum usable switching frequency is considerably higher. switching time is independent of temperature. also, at higher frequencies, the use of smaller and lighter components (transformer, filter choke, filter capacitor) reduces overall component cost while using less space for more efficient packaging at lower weight. the mosfet has purely capacitive input impedance. no dc current is required. it is important to keep in mind the drain current of the fet has a negative temperature coefficient. increase in temperature causes higher onresistance and greater leakage current. v ds(on) should be low to minimize power dissipation at a given i d , and v gs should be high to accomplish this. mosfet switching times are determined by device capacitance, stray capacitance, and the impedance of the gate drive circuit. thus the gate driving circuit must have high momentary peak current sourcing and sinking capability for switching the mosfet. the input capacitance, output capacitance and reversetransfer capacitance also increase with increased device current rating. two considerations complicate the task of estimating switching times. first, since the magnitude of the input capacitance, c iss , varies with v ds , the rc time constant determined by the gatedrive impedance and c iss changes during the switching cycle. consequently, computation of the rise time of the gate voltage by using a specific gatedrive impedance and input capacitance yields only a rough estimate. the second consideration is the effect of the amillero capacitance, c rss , which is referred to as c dg in the following discussion. for example, when a device is on, v ds(on) is fairly small and v gs is about 12 v. c dg is charged to v ds(on) v gs , which is a negative potential if the drain is considered the positive electrode. when the drain is aoffo, c dg is charged to quite a different potential. in this case the voltage across c dg is a positive value since the potential from gatetosource is near zero volts and v ds is essentially the drain supply voltage. during turnon and turnoff, these large swings in gatetodrain voltage tax the current sourcing and sinking capabilities of the gate drive. in addition to charging and discharging c gs , the gate drive must also supply the displacement current required by c dg (i gate = c dg dv dg /dt). unless the gatedrive impedance is very low, the v gs waveform commonly plateaus during rapid changes in the draintosource voltage. the most important aspect of fet performance is the static draintosource onresistance (r ds(on) ), which effects regulator efficiency and fet thermal management requirements. the onresistance determines the amount of current a fet can handle without excessive power dissipation that may cause overheating and potentially catastrophic failure. as the drain current rises, especially above the continuous rating, the onresistance also increases. its positive temperature coefficient is between +0.6%/c and +0.85%/c. the higher the onresistance the larger the conduction loss is. additionally, the fet gate charge should be low in order to minimize switching losses and reduce power dissipation. both logic level and standard fets can be used. voltage applied to the fet gates depends on the application circuit used. both upper and lower gate driver outputs are specified to drive to within 1.5 v of ground when in the low state and to within 2.0 v of their respective bias supplies when in the high state. in practice, the fet gates will be driven railtorail due to overshoot caused by the capacitive load they present to the controller ic. step 7a: selection of the switching (upper) fet the designer must ensure that the total power dissipation in the fet switch does not cause the power component's junction temperature to exceed 150 c. the maximum rms current through the switch can be determined by the following formula: i rms(h) i l(peak) 2 ( i l(peak) i l(valley) ) i l(valley) 2 d 3.0
where: i rms(h) = maximum switching mosfet rms current; i l(peak) = inductor peak current; i l(valley) = inductor valley current; d = duty cycle.
cs51312 http://onsemi.com 17 once the rms current through the switch is known, the switching mosfet conduction losses can be calculated: p rms(h) i rms(h) 2 r ds(on) where: p rms(h) = switching mosfet conduction losses; i rms(h) = maximum switching mosfet rms current; r ds(on) = fet draintosource onresistance the upper mosfet switching losses are caused during mosfet switchon and switchoff and can be determined by using the following formula: p swh p swh(on) p swh(off) v in i out (t rise t fall ) 6.0t where: p swh(on) = upper mosfet switchon losses; p swh(off) = upper mosfet switchoff losses; v in = input voltage; i out = load current; t rise = mosfet rise time (from fet manufacturer's switching characteristics performance curve); t fall = mosfet fall time (from fet manufacturer's switching characteristics performance curve); t = 1/f sw = period. the total power dissipation in the switching mosfet can then be calculated as: p hfet ( total ) p rmsh p swh ( on ) p swh ( off ) where: p hfet(total) = total switching (upper) mosfet losses; p rmsh = upper mosfet switch conduction losses; p swh(on) = upper mosfet switchon losses; p swh(off) = upper mosfet switchoff losses. once the total power dissipation in the switching fet is known, the maximum fet switch junction temperature can be calculated: t j t a ( p hfet(total) r ja ) where: t j = fet junction temperature; t a = ambient temperature; p hfet(total) = total switching (upper) fet losses; r q ja = upper fet junctiontoambient thermal resistance. step 7b: selection of the synchronous (lower) fet the switch conduction losses for the lower fet can be calculated as follows: p rmsl i rms 2 r ds(on) i out (1.0 d)
2 r ds(on) where: p rmsl = lower mosfet conduction losses; i out = load current; d = duty cycle; r ds(on) = lower fet draintosource onresistance. the synchronous mosfet has no switching losses, except for losses in the internal body diode, because it turns on into near zero voltage conditions. the mosfet body diode will conduct during the nonoverlap time and the resulting power dissipation (neglecting reverse recovery losses) can be calculated as follows: p swl v sd i load nonoverlap time f sw where: p swl = lower fet switching losses; v sd = lower fet sourcetodrain voltage; i load = load current nonoverlap time = gate(l)togate(h) or gate(h)togate(l) delay (from cs51312 data sheet electrical characteristics section); f sw = switching frequency. the total power dissipation in the synchronous (lower) mosfet can then be calculated as: p lfet(total) p rmsl p swl where: p lfet(total) = synchronous (lower) fet total losses; p rmsl = switch conduction losses; p swl = switching losses. once the total power dissipation in the synchronous fet is known the maximum fet switch junction temperature can be calculated: t j t a ( p lfet(total) r ja ) where: t j = mosfet junction temperature; t a = ambient temperature; p lfet(total) = total synchronous (lower) fet losses; r q ja = lower fet junctiontoambient thermal resistance. step 8: control ic power dissipation the power dissipation of the ic varies with the mosfets used, v cc , and the cs51312 operating frequency. the average mosfet gate charge current typically dominates the control ic power dissipation. the ic power dissipation is determined by the formula: p controlic i cc1 v cc1 p gate(h) p gate(l) where: p controlic = control ic power dissipation; i cc1 = ic quiescent supply current; v cc1 = ic supply voltage; p gate(h) = upper mosfet gate driver (ic) losses; p gate(l) = lower mosfet gate driver (ic) losses.
cs51312 http://onsemi.com 18 the upper (switching) mosfet gate driver (ic) losses are: p gate(h) q gate(h) f sw v gate(h) where: p gate(h) = upper mosfet gate driver (ic) losses; q gate(h) = total upper mosfet gate charge; f sw = switching frequency; v gate(h) = upper mosfet gate voltage. the lower (synchronous) mosfet gate driver (ic) losses are: p gate(l) q gate(l) f sw v gate(l) where: p gate(l) = lower mosfet gate driver (ic) losses; q gate(l) = total lower mosfet gate charge; f sw = switching frequency; v gate(l) = lower mosfet gate voltage. the junction temperature of the control ic is primarily a function of the pcb layout, since most of the heat is removed through the traces connected to the pins of the ic. step 9: slope compensation voltage regulators for today's advanced processors are expected to meet very stringent load transient requirements. one of the key factors in achieving tight dynamic voltage regulation is low esr at the cpu input supply pins. low esr at the regulator output results in low output voltage ripple. the consequence is, however, that there's very little voltage ramp at the control ic feedback pin (v fb ) and regulator sensitivity to noise and loop instability are two undesirable effects that can surface. the performance of the cs51312based cpu v cc(core) regulator is improved when a fixed amount of slope compensation is added to the output of the pwm error amplifier (comp pin) during the regulator offtime. referring to figure 14, the amount of voltage ramp at the comp pin is dependent on the gate voltage of the lower (synchronous) fet and the value of resistor divider formed by r1and r2. v slopecomp v gate(l) r2 r1 r2 1.0 e t where: v slopecomp = amount of slope added; v gate(l) = lower mosfet gate voltage; r1, r2 = voltage divider resistors; t = t off (switch offtime); t = rc constant determined by c1 and the parallel combination of r1, r2 (figure 14), neglecting the low driver output impedance. figure 14. small rc filter provides the proper voltage ramp at the beginning of each ontime cycle 16 to synchronous fet c comp r1 r2 c1 12 cs51312 comp gate(l) the artificial voltage ramp created by the slope compensation scheme results in improved control loop stability provided that the rc filter time constant is smaller than the offtime cycle duration (time during which the lower mosfet is conducting). it is important that the series combination of r1 and r2 is high enough in resistance to avoid loading the gate(l) pin. step 10: selection of current limit filter components in some applications, the current limit comparator may falsely trigger due to noise, load transients, or high inductor ripple currents. a filter circuit such as the one shown in figure 15 can be added to prevent this. the rc time constant of this filter is equal to (r fb + r out ) c sense . increasing the rc time constant will reduce the sensitivity of the circuit, but increase the time required to detect an overcurrent condition. the value of r fb + r out should be kept to 510 w or lower to avoid significant dc offsets due to the v fb and v out bias currents. figure 15. current limit filter circuit + v in v out r sense r out r fb c sense gate(h) gate(l) v fb v out
cs51312 http://onsemi.com 19 adroopo resistor for adaptive voltage positioning and current limit adaptive voltage positioning is used to help keep the output voltage within specification during load transients. to implement adaptive voltage positioning a adroop resistoro must be connected between the output inductor and output capacitors and load. this resistor carries the full load current and should be chosen so that both dc and ac tolerance limits are met. in order to determine the droop resistor value the nominal voltage drop across it at full load has to be calculated. this voltage drop has to be such that the output voltage at full load is above the minimum dc tolerance spec: v droop(typ) v dac(min) v dc(min) 1.0 r droop(tolerance) current limit the current limit setpoint has to be higher than the normal full load current. attention has to be paid to the current rating of the external power components as these are the first to fail during an overload condition. the mosfet continuous and pulsed drain current rating at a given case temperature has to be accounted for when setting the current limit trip point. nominal current limit setpoint from the overcurrent detection data in the electrical characteristics table: v th(typ) 86 mv i cl(nom) v th(typ) r sense(nom) design rules for using a droop resistor the basic equation for laying an embedded resistor is: r ar l a or r l (w t) where: a = w t = crosssectional area; r = the copper resistivity ( mw mil); l = length (mils); w = width (mils); t = thickness (mils). an embedded pc trace resistor has the distinct advantage of near zero cost implementation. however, this droop resistor can vary due to three reasons: 1) the sheet resistivity variation caused by variation in the thickness of the pcb layer; 2) the mismatch of l/w; and 3) temperature variation. 1) sheet resistivity for one ounce copper, the thickness variation is typically 1.26 mil to 1.48 mil. therefore the error due to sheet resistivity is: 1.48 1.26 1.37 8.0% 2) mismatch due to l/w the variation in l/w is governed by variations due to the pcb manufacturing process. the error due to l/w mismatch is typically 1.0%. 3) thermal considerations due to i 2 r power losses the surface temperature of the droop resistor will increase causing the resistance to increase. also, the ambient temperature variation will contribute to the increase of the resistance, according to the formula: r r 20 [1.0 20 (t 20)] where: r 20 = resistance at 20 c; a = 0.00393/ c t= operating temperature; r = desired droop resistor value. for temperature t = 50 c, the % r change = 12%. droop resistor tolerance tolerance due to sheet resistivity variation 8.0% tolerance due to l/w error 1.0% tolerance due to temperature variation 12% total tolerance for droop resistor 21% droop resistor length, width, and thickness the minimum width and thickness of the droop resistor should primarily be determined on the basis of the currentcarrying capacity required, and the maximum permissible droop resistor temperature rise. pcb manufacturer design charts can be used in determining currentcarrying capacity and sizes of etched copper conductors for various temperature rises above ambient. thermal management thermal considerations for power mosfets in order to maintain good reliability, the junction temperature of the semiconductor components should be kept to a maximum of 150 c or lower. the thermal impedance (junction to ambient) required to meet this requirement can be calculated as follows: thermal impedance t j(max) t a power a heatsink may be added to to220 components to reduce their thermal impedance. a number of pc board layout techniques such as thermal vias and additional copper foil area can be used to improve the power handling capability of surface mount components. emi management as a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. when designing for compliance with emi/emc regulations, additional components may be added to reduce noise emissions. these
cs51312 http://onsemi.com 20 components are not required for regulator operation and experimental results may allow them to be eliminated. the input filter inductor may not be required because bulk filter and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. placement of the power component to minimize routing distance will also help to reduce emissions. layout guidelines when laying out the cpu buck regulator on a printed circuit board, the following checklist should be used to ensure proper operation of the cs51312. 1. rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors are major concerns for a good layout. 2. keep high currents out of sensitive ground connections. 3. avoid ground loops as they pick up noise. use star or single point grounding. 4. for high power buck regulators on doublesided pcbs a single ground plane (usually the bottom) is recommended. 5. even though double sided pcbs are usually suf ficient for a good layout, fourlayer pcbs are the optimum approach to reducing susceptibility to noise. use the two internal layers as the power and gnd planes, the top layer for power connections and component vias, and the bottom layer for the noise sensitive traces. 6. keep the inductor switching node small by placing the output inductor, switching and synchronous fets close together. 7. the mosfet gate traces to the ic must be as short, straight, and wide as possible. 8. use fewer, but larger output capacitors, keep the capacitors clustered, and use multiple layer traces with heavy copper to keep the parasitic resistance low. 9. place the switching mosfet as close to the +5.0 v input capacitors as possible. 10. place the output capacitors as close to the load as possible. 11. place the v fb , v out filter resistors (510 w ) in series with the v fb and v out pins as close as possible to the pins. 12. place the c off and comp capacitors as close as possible to the c off and comp pins. 13. place the current limit filter capacitor between the v fb and v out pins, as close as possible to the pins. 14. connect the filter components of the following pins: v fb , v out , c off , and comp to the gnd pin with a single trace, and connect this local gnd trace to the output capacitor gnd. 15. the adroopo resistor (embedded pcb trace) has to be wide enough to carry the full load current. 16. place the v cc bypass capacitor as close as possible to the ic.
cs51312 http://onsemi.com 21 figure 16. additional application circuit, 5.0 v/12 v to 2.0 v/19 a converter 1.2 m h 3.3 m w comp v id0 v id1 v id2 v id3 v id4 gate(h) gate(l) v fb v out ovp cs51312 v cc1 pwrgd v cc2 10 k +12 v fs70vsj03 fs70vsj03 gnd pwrgd ovp c off 0.1 m f 0.01 m f 100 w 680 pf 1.0 m f +5.0 v 1200 m f/10 v 3 510 w 510 w 0.1 m f 1200 m f/10 v 5 v cc(core) 2.0 v @ 19 a
cs51312 http://onsemi.com 22 package dimensions so16 d suffix case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 package thermal data parameter so16 unit r q jc typical 28 c/w r q ja typical 115 c/w
cs51312 http://onsemi.com 23 notes
cs51312 http://onsemi.com 24 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs51312/d v 2 is a trademark of switch power, inc. pentium is a registered trademark of intel corporation. north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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